The handheld consumer products market is aggressive in the miniaturization of portable electronics. Primarily driven at present by the cellular phone and digital assistant markets, manufacturers of these devices are challenged by ever shrinking formats and the demand for more PC-like functionality. This challenge asserts pressure on surface mount component manufacturers to design their products to command the smallest area possible. By doing so, this allows portable electronics designers to incorporate additional functions within a device without increasing the overall product size.
In Chip Scale Packaging (CSP) technologies, manufacturers strive to bring the package size as close as possible to the size of the semiconductor chip. The electronics industry has accepted the Joint Electronic Device Engineering Council (JEDEC) defined Quad Flat Pack (QFP) and Quad Flat Pack No Lead (QFN) outlines as good alternatives for low cost chip scale packages. In typical QFP and QFN packages, the lower surface of a semiconductor chip is attached to a metal lead frame. Wire bonds are then used to connect circuitry located on the front side of the chip to individual leads on the lead frame. The chip and lead frame are subsequently encapsulated by an epoxy resin to form an assembled component.
FIG. 1 shows a partial cross-sectional view of a conventional QFP package 10 including a lead frame 11. Lead frame 11 includes a flag portion 13 for supporting a semiconductor chip 14 and a lead 16. A wire bond 17 connects semiconductor chip 14 to lead 16. An epoxy layer 19 covers semiconductor chip 14 and lead frame 11 except for portions of lead 16, which extend in a gull wing shape from the sides of the package. Although only a portion of QFP package 10 is shown, QFP packages typically are square or rectangular with leads 16 extending from all four sides of the package.
FIG. 2 shows a partial cross-sectional view of a conventional QFN package 20 including lead frame 21. Lead frame 21 comprises a flag portion 23 for supporting semiconductor chip 14, and leads 26. Wire bond 17 connects semiconductor chip 14 to a lead 26. Epoxy layer 19 covers semiconductor chip 14 and portions of lead frame 21, while leaving lower portions of flag 23 and lead 26 exposed. In the QFN package, the leads (e.g., lead 26) terminate at the edge of the package to provide a smaller package footprint. Although only a portion of QFN package 20 is shown, QFN packages typically are square or rectangular with leads 26 present on all four sides of the lower surface of the package. FIG. 3 shows an isometric and cut-away view of device 20. The Dual Flat No Lead (DFN) package is another chip scale package similar to the QFN except that the DFN only has leads on two opposing sides of the lower surface of the package.
There are several advantages to QFP, QFN, and DFN packages including large die size to package footprint ratio, matrix lead frame arrays that allow for easier assembly, and established automated assembly tools. However, there are several problems associated with these packages including poor heat transfer capability for high power device applications and very limited mounting options for attaching the packages to next levels of assembly including heat sinks and printed circuit boards.
Accordingly, a need exists for a package structure and method of assembly that is manufacturable on existing chip scale assembly platforms that use lead frames (e.g., QFP/QFN/DFN platforms), that supports high power applications, that supports multiple die options, and that has more flexible attachment options for connecting to next levels of assembly.